CPU design is the design engineering task of creating a central processing unit (CPU), a component of computer hardware. It is a sub field of electronics engineering and computer engineering. There are several different markets in which CPUs are used. Since each of these markets differs in their requirements for CPUs, the devices designed for one market are in most cases inappropriate for the other markets. These single function devices differ from the more familiar general purpose CPUs in several ways: High performance processing capability of processor core unit is important need of such processing devices. Digital processing architecture processes multiple tasks simultaneously to achieve maximum performance of any multitasking system. High bandwidth capacity is another consideration in choosing any processor. Therefore, bandwidth during DMA transfer is quite high to get superior operation speed thoroughly. Not only text data or commands but also it is capable of handling wide varieties of other formats including audio and video. It uses IEEE 1180 rounding operation for this purpose. Moreover, video compression algorithm is implemented in the software application that allows OEM to adopt standards and new functional requirements of any system. This article has presented a DSE methodology that can optimize an FPCT for a given set of benchmarks; the I/O utilization metric, was introduced to reduce the number of FPCT architectures are synthesized during the DSE, while providing high confidence to the user that the remaining design points are among the best. Efficient control processing is another advantage of DSP processor. For this, it uses RISC instructions set to process and manipulate any kind of instructions or command speedily. It uses hierarchical memory structure with two caches namely L1 and L2. L1 cache stores instructions and SRAM data. L2 also stores instructions and data but is applicable on only selected models. These both caches interact directly with DMA chip, called direct memory access unit. Processor architecture also offers a variety of benefits most often seen in RISC control processors. These features include powerful and flexible hierarchical memory architecture, superior code density, and a variety of micro controller style peripherals. Superior code density is provided by such models to achieve huge data buffering limit. Also, dynamic power management functionality is added advantage. This delivers code density benchmark which is mostly used by industrial RISC processors worldwide. All multitasking processors have multiple, independent DMA controllers that support automated data transfers with minimal overhead from the processor core. DMA transfers can occur between the internal memories and any of the many DMA capable peripherals.